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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
FEATURES
* Eight LVDS outputs * Crystal oscillator interface * Supports the following output frequencies: 100MHz or 125MHz * VCO: 500MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) * Full 3.3V supply modes * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS844008-16 is an 8 output LVDS Synthesizer optimized to generate PCI Express HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz parallel resonant crystal, the following frequencies can be generated based on F_SEL pin: 100MHz or 125MHz. The ICS844008-16 uses ICS' 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting PCI Express jitter requirements. The ICS844008-16 is packaged in a 32-pin LQFP package.
IC S
FREQUENCY SELECT FUNCTION TABLE
Input Input Frequency (MHz) 25MHz 25MHz M Divider Value 20 20 N Divider Value 4 5 M/N Divider Value 5 4 Output Frequency (MHz) 12 5 100
PIN ASSIGNMENT
XTAL_OUT nPLL_SEL XTAL_IN VDDA GND OE1 OE2 VDD
F_SEL 0 1
32 31 30 29 28 27 26 25 Q0 nQ0 VDD Q1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F_SEL Q3 nQ3 VDD GND Q4 nQ4 MR
24
Q7 nQ7 VDD Q6 nQ6 GND Q5 nQ5
ICS844008-16
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
23 22 21 20 19 18 17
BLOCK DIAGRAM
nPLL_SEL
Pulldown
nQ1 Q0 nQ0 Q1 GND Q2 nQ2
1
XTAL_IN
25MHz
nQ1 Q2
OSC
XTAL_OUT
Phase Detector
VCO
500MHz
(w/25MHz Reference)
0
/4 /5
nQ2 Q3 nQ3
M = /20 (fixed)
OE1
Pullup
Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7
MR Pulldown F_SEL OE2
Pullup Pullup
nQ7
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844008AY -16 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 1, 2006
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Type Description Differential output pair. LVDS interface levels. Core supply pin. Differential output pair. LVDS interface levels. Power supply ground. Differential output pair. LVDS interface levels. Pullup Frequency select pin LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 12, 22, 27 4, 5 6, 13, 19, 29 7, 8 9 10, 11 14, 15 16 17, 18 20, 21 23, 24 25 Name Q0, nQ0 VDD Q1, nQ1 GND Q2, nQ2 F_SEL Q3, nQ3 Q4, nQ4 MR nQ5, Q5 nQ6, Q6 nQ7, Q7 VDDA Output Power Ouput Power Output Input Output Output Input Output Output Output Power Pulldown
Analog supply pin. Selects between the PLL and REF_CLK as input to the dividers. When LOW, Pulldselects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL 26 nPLL_SEL Input own Bypass). LVCMOS/LVTTL interface levels. Output enable for Q5/nQ5:Q7/nQ7 outputs. 28 OE2 Input Pullup LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_OUT, 30, 31 Input XTAL_IN is the input. XTAL_IN Output enable for Q0/nQ0:Q4/nQ4 outputs. 32 OE1 Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input PullUP Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3A. OE1 FUNCTION TABLE
Input OE1 0 1 Outputs Q0:Q4, nQ0:nQ4 Places outputs in Hi-Z state Normal operation
TABLE 3B. OE2 FUNCTION TABLE
Input OE2 0 1 Outputs Q5:Q7, nQ5:nQ7 Places outputs in Hi-Z state Normal operation
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, JA 47.9C/W (0 lfpm)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 285 12 Maximum 3.465 3.465 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current MR, nPLL_SEL OE1, OE2, F_SEL MR, nPLL_SEL OE1, OE2, F_SEL Test Conditions VDD = 3.3V VDD = 3.3V VDD = VIN = 3.465 VDD = VIN = 3.465 VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 440 40 1.4 50 Maximum Units mV mV V mV
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum 22.4 Typical 25 Maximum 27.2 100 50 7 Units MH z ppm pF W
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Par ts per Million (ppm); NOTE 1 Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
Drive Level 100 NOTE: Characterized using an18pF parallel resonant crystal. NOTE 1: When used with recommended 50ppm crystal and external trim caps adjusted for user PC board.
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO70C
Symbol fOUT tsk(o) tjit(cc) tjit(O) t R / tF Parameter Output Frequency Output Skew; NOTE 1, 2 Cycle-to-Cycle Jitter RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time 125MHz, (1.875MHz - 20MHz) 100MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions FSEL = 0 FSEL = 1 Minimum Typical 125 100 TBD 40 0.44 0.44 450 Maximum Units MHz MHz ps ps ps ps ps %
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDD/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
AT
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50 -60
125MHZ AT 3.3V
PCI Express Jitter Filter 125MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.44ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 1k 10k
Phase Noise Result by adding PCI Express Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
Noise Power
Qx
3.3V5% POWER SUPPLY + Float GND -
SCOPE
LVDS
nQx
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
RMS PHASE JITTER
nQ0:nQ7 Q0:nQ7

tcycle n
tcycle
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0:nQ7 80% Q0:Q7 80% VSW I N G
t
PERIOD
t PW
Clock Outputs
20% tR tF
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out DC Input
OUTPUT RISE/FALL TIME
VDD out
out
VOS/ VOS
out
OFFSET VOLTAGE SETUP
844008AY -16
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. A FEBRUARY 1, 2006
LVDS
DC Input
LVDS
100
VOD/ VOD
n+1
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
20%
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844008-16 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844008-16 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008-16. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844008-16 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
*
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (285mA + 12mA) = 1029mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.029W * 42.1C/W = 113.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 32-LEAD LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844008-16 is: 2597
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A FEBRUARY 1, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844008-16
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Marking Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS844008AY-16 ICS844008AY-16T ICS844008AY-16LF ICS844008AY-16LFT ICS844008A16 ICS844008A16 TBD TBD
NOTE: par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844008AY -16
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